Senior FPGA_AIE Engineer

Chantilly, United StatesOn-site

Responsibilities

Responsibilities: responsibilities are as follows: - Design and test high-speed FPGA systems for satellite communication systems. - Build with AMD Versal hard IP such as AIE, NoC, CIPS, MRMAC, and DDR controllers. - Model and implement DSP algorithms in RTL or AMD AIE/AIE-ML processors. - Implement device driver software in C, C++, or other languages for a Linux environment. - Develop and maintain documentation and ICDs for in-house IP blocks and other related components. Minimum

experience designing and developing custom software-defined radio (SDR) platforms.
Aspects of the position require an understanding of FPGA hardware, firmware, digital signal processing, and algorithms for SDR-based satellite communication.
As a Senior FPGA_AIE Engineer, you will support the development of custom radio platforms for the primary (cellular service link) and secondary (TT&C / feeder link) communication links.
Responsibilities As a Senior FPGA_AIE Engineer, your core
Requirements - A Bachelor’s degree (or higher) in Electrical Engineering, Computer Engineering, or related field. - At least five years of recent related
experience working with Xilinx/Altera FPGAs. - Proficient in at least one of the following: - SystemVerilog programming - AMD Versal SoC programming - AIE-ML or AIE programming, specifically intrinsic based development. Preferred Qualifications -
Experience with timing closure for high utilization FPGA builds. -
Experience with FPGA SoCs and Bare Metal or Petalinux design flows. -
Experience with UVM or hardware in the loop testing methodologies. -
Experience with RFICs and multi chip synchronization. -
Experience with high-speed interfaces such as JESD204C and high speed Ethernet. - Knowledge of the physical layer of cellular standards (e.g., GSM, LTE, 5G) is a plus. ITAR

Learn about ITAR here. https://www.pmddtc.state.gov/ddtc_public?id=ddtc_kb_article_page&sys_id=24d528fddbfc930044f9ff621f961987 Job Location Chantilly, VA